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This queue is for tickets about the Verilog-Perl CPAN distribution.

Maintainer(s)

WSNYDER

Bugs

ID Subject Status Severity Last Updated Broken in Fixed in
27624 Verilog::Netlist now cannot recognize builtins (primitives?) resolved Important 12 years ago 3.001
51024 Minimum version of Pod::Usage should be 1.34 resolved Normal 10 years ago 3.221
43138 parse error with nested list resolved Important 11 years ago 3.110
35161 Problem building Verilog-Perl 3.024 resolved 11 years ago
25833 Fails to parse first statement after null port list resolved Important 13 years ago 2.341
2.372
24345 lint returns errors on supply nets connected to normal (wire) pins resolved Normal 13 years ago 2.370
34575 Bug in Verilog-Perl - MIN:TYP:MAX delays in assign resolved 12 years ago
13462 Failure to correctly parse buses of concatenated bits resolved Important 13 years ago 2.316
31198 typo in VParseLex.l resolved Normal 12 years ago
29128 Error making Verilog-Perl-3.011 resolved 11 years ago
3285 Compile error with gcc at "assert" resolved Important 15 years ago 2.225
81501 Test failures due to hash randomisation in perl 5.17.6 resolved Important 7 years ago 3.317
48226 compile failures on multiple OSes with perl-5.8.8 resolved Critical 10 years ago 3.212
43116 typedef parse error for system verilog resolved Critical 11 years ago 3.110
34948 nested macros are not expanded correctly if a macro has arguments ... resolved 11 years ago
24248 Netlist module converts "supply" statements to "wire" resolved Important 13 years ago 2.361
34574 Bug in Verilog-Perl resolved 12 years ago
11351 Spurious parse errors with a file with many blank lines resolved Normal 15 years ago 2.311
30180 (No subject) resolved Important 12 years ago
28496 Verilog Perl does not parse widths correctly resolved 12 years ago
55460 An example in Verilog::EditFiles doesn't work resolved Normal 10 years ago 3.231
47030 adapt Verilog::Getopt to recent releases of Getopt::Long resolved Important 10 years ago 3.210
24552 wire declaration is wrong when add new net resolved 13 years ago
34649 Output Register init value resolved 12 years ago
34429 macro with systemVerilog lexical delimiter fails if white spaces present in macro calling resolved 12 years ago
29546 SystemVerilog not supported - packages Error resolved 11 years ago
11248 directories return in resolve_filename instead of filenames resolved Important 15 years ago 2.302
25109 Cannot do `define error resolved Normal 13 years ago 2.341
2.371
2.373
26967 Use Math::BigInt for constants > 32 bits resolved Important 12 years ago 2.373 2.380
27067 Time variable in a delay parses as instance resolved Normal 12 years ago 2.373 3.000
27045 signal_decl not called for definitions in port list resolved Normal 12 years ago 2.373 3.000
27036 Problem with list of memories resolved Normal 12 years ago 2.373 3.000
27009 Wire with drive strength does not parse resolved Normal 12 years ago 2.373 3.000
26970 Parameter list parses incorrectly resolved Important 12 years ago 2.373 3.000
27072 output reg declaration should call signal_decl twice resolved Normal 12 years ago 2.373 3.000
27066 function not called for integer function definition resolved Normal 12 years ago 2.373 3.000
27039 signal_decl not called for integer resolved Important 12 years ago 2.373 3.000
27013 Connecting 0 to pin doesn't work resolved Important 12 years ago 2.373 3.000
26997 Last pin callback not called resolved Important 12 years ago 2.373 3.000
26969 Arrayed instances fail to parse resolved Important 12 years ago 2.373 3.000
26940 Erroneous connection to pin callback resolved Important 12 years ago 2.373 3.000
27070 Verilog::Preproc inserts extra space resolved Normal 12 years ago 2.373 3.000
27062 instant not called for primitive instance without instance name resolved Normal 12 years ago 2.373 3.000
27037 Scalar memory parsed as vector resolved Normal 12 years ago 2.373 3.000
27010 Negation of signal not passed to pin resolved Important 12 years ago 2.373 3.000
26972 Request option to call signal_decl for signals in tasks/functions resolved Normal 12 years ago 2.373 3.000
26968 signal_decl not called for wire resolved Important 12 years ago 2.373 3.000
26141 Combined wire declaration/assignments resolved Important 12 years ago 2.372
2.373
3.000
24247 Quoted cell names absorb terminating whitespace resolved Important 12 years ago 2.361 3.000
39654 Test 04critic written badly resolved Normal 11 years ago 3.042 3.043

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