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This queue is for tickets about the Verilog-Perl CPAN distribution.

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The Basics
Id: 43116
Status: resolved
Priority: 0/
Queue: Verilog-Perl

People
Owner: Nobody in particular
Requestors: devendra.singh [...] lsi.com
Cc:
AdminCc:

Bug Information
Severity: Critical
Broken in: 3.110
Fixed in: (no value)



Subject: typedef parse error for system verilog
Download (untitled) / with headers
text/plain 538b
Hi, It was trying to parse system verilog files attached with vhier, but get the following error. Probably the parser is not able to get the typedef's from the package file. I will appreciate if this can be resolved as I wish to use this in my script. vhier temp_mod.sv %Error: temp_mod.sv:8: syntax error, unexpected "IDENTIFIER", expecting ')' %Error: temp_mod.sv:20: syntax error, unexpected "output", expecting "IDENTIFIER" %Error: temp_mod.sv:29: syntax error, unexpected ')', expecting ',' or ';' Exiting due to errors
Subject: temp_pkg.sv
Download temp_pkg.sv
text/plain 289b
package temp_pkg; typedef enum logic {FALSE, TRUE} false_true; typedef logic [1:0] two_bits; typedef logic [2:0] three_bits; typedef logic [3:0] nibble; typedef logic [4:0] five_bits; typedef logic [5:0] six_bits; typedef logic [6:0] seven_bits; typedef logic [7:0] byte_wide; endpackage
Subject: temp_mod.sv
Download temp_mod.sv
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module temp_mod ( //Inputs input sys_lclk, input sys_lrst, input scram_enable, input gen_speed, input two_bits rx_invalid, input two_bits rx_par, input rxStart_in, input two_bits Char_in, input Valid_in, input word_wide rx_data, input [22:0] init_seed, input last_eieos_bit, input last_fts_bit, //Outputs output logic [22:0] flsr, output scr_invalid0, scr_invalid1, output scr_par0, scr_par1, output word_wide aligndata, output two_bits rxSyncChar, output rxStart, output rxValid, output logic didle_det0, didle_det1 ); import temp_pkg::byte_wide; import temp_pkg::nibble; import temp_pkg::two_bits; import temp_pkg::word_wide; import temp_pkg::false_true; import temp_pkg::FALSE; import temp_pkg::TRUE; endmodule
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text/plain 145b
I am working on this support along with some other SystemVerilog features, but it will probably be a few weeks, as typedefs are very complicated.
Download (untitled) / with headers
text/plain 165b
This is fixed in the beta candidate in GIT at veripool.org. It will be in 3.200. If you have additional issues please use the bug tracker at veripool.org, thanks.


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