Skip Menu |

Preferred bug tracker

Please visit the preferred bug tracker to report your issue.

This queue is for tickets about the Verilog-Perl CPAN distribution.

Report information
The Basics
Id: 43116
Status: resolved
Priority: 0/
Queue: Verilog-Perl

Owner: Nobody in particular
Requestors: devendra.singh [...]

Bug Information
Severity: Critical
Broken in: 3.110
Fixed in: (no value)

Subject: typedef parse error for system verilog
Download (untitled) / with headers
text/plain 538b
Hi, It was trying to parse system verilog files attached with vhier, but get the following error. Probably the parser is not able to get the typedef's from the package file. I will appreciate if this can be resolved as I wish to use this in my script. vhier %Error: syntax error, unexpected "IDENTIFIER", expecting ')' %Error: syntax error, unexpected "output", expecting "IDENTIFIER" %Error: syntax error, unexpected ')', expecting ',' or ';' Exiting due to errors
text/plain 289b
package temp_pkg; typedef enum logic {FALSE, TRUE} false_true; typedef logic [1:0] two_bits; typedef logic [2:0] three_bits; typedef logic [3:0] nibble; typedef logic [4:0] five_bits; typedef logic [5:0] six_bits; typedef logic [6:0] seven_bits; typedef logic [7:0] byte_wide; endpackage
text/plain 1k
module temp_mod ( //Inputs input sys_lclk, input sys_lrst, input scram_enable, input gen_speed, input two_bits rx_invalid, input two_bits rx_par, input rxStart_in, input two_bits Char_in, input Valid_in, input word_wide rx_data, input [22:0] init_seed, input last_eieos_bit, input last_fts_bit, //Outputs output logic [22:0] flsr, output scr_invalid0, scr_invalid1, output scr_par0, scr_par1, output word_wide aligndata, output two_bits rxSyncChar, output rxStart, output rxValid, output logic didle_det0, didle_det1 ); import temp_pkg::byte_wide; import temp_pkg::nibble; import temp_pkg::two_bits; import temp_pkg::word_wide; import temp_pkg::false_true; import temp_pkg::FALSE; import temp_pkg::TRUE; endmodule
Download (untitled) / with headers
text/plain 145b
I am working on this support along with some other SystemVerilog features, but it will probably be a few weeks, as typedefs are very complicated.
Download (untitled) / with headers
text/plain 165b
This is fixed in the beta candidate in GIT at It will be in 3.200. If you have additional issues please use the bug tracker at, thanks.

This service is sponsored and maintained by Best Practical Solutions and runs on infrastructure.

Please report any issues with to