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This queue is for tickets about the Verilog-Perl CPAN distribution.

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Id: 34575
Status: resolved
Priority: 0/
Queue: Verilog-Perl

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Owner: Nobody in particular
Requestors: martin [...] scharrer-online.de
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Subject: Bug in Verilog-Perl - MIN:TYP:MAX delays in assign
Date: Mon, 31 Mar 2008 16:31:36 +0100
To: bug-Verilog-Perl [...] rt.cpan.org
From: Martin Scharrer <martin [...] scharrer-online.de>
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Hello, I'm using the tool 'vhier' included in Verilog-Perl which uses Verilog::Language to print the hierarchy of my Verilog files. My code is mostly Verilog1995 with some minor exceptions in some test-bench files where I use the 'generate' block. The used versions are Perl 5.8.8 vhier: # $Id: vhier 49328 2008-01-07 16:28:25Z wsnyder $ Verilog-Perl-3.023 from CPAN The parser can't handle assignments which uses the MIN:TYP:MAX delay syntax for falling and rising edges. Please see the example below: module test; wire a,b,c,d; assign #(0,0) a = 1; // Works assign #(0:1:2) b = 1; // Works assign #(0:1:2,0:1:2) c = 1; // Does not work assign #(0:1:2,0) d = 1; // Does not work endmodule %Error: test.v:5: syntax error, unexpected ',', expecting ')' Exiting due to errors This is valid Verilog code in my opinion. Thank you, Martin Scharrer
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Thanks for the case. This will be fixed in the next release. The patch is below: =================================================================== --- Parser/VParseBison.y (revision 52625) +++ Parser/VParseBison.y (working copy) @@ -747,10 +747,9 @@ ; delay: '#' dlyTerm { } /* ignored */ - | '#' '(' dlyInParen ')' { } /* ignored */ - | '#' '(' dlyInParen ',' dlyInParen ')' { } /* ignored */ - | '#' '(' dlyInParen ',' dlyInParen ',' dlyInParen ')' { } /* ignored */ - | '#' '(' dlyInParen ':' dlyInParen ':' dlyInParen ')' { } /* ignored */ + | '#' '(' minTypMax ')' { } /* ignored */ + | '#' '(' minTypMax ',' minTypMax ')' { } /* ignored */ + | '#' '(' minTypMax ',' minTypMax ',' minTypMax ')' { } /* ignored */ ; dlyTerm: yaID { } @@ -759,7 +758,9 @@ | yaTIMENUM { } ; -dlyInParen: expr { } +// IEEE: mintypmax_expression and constant_mintypmax_expression +minTypMax: expr { } + | expr ':' expr ':' expr { } ; sigAndAttr: sigId sigAttrListE { $<fl>$=$<fl>1; $$=$1; }


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