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This queue is for tickets about the Verilog-Perl CPAN distribution.

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The Basics
Id: 30180
Status: resolved
Priority: 0/
Queue: Verilog-Perl

People
Owner: Nobody in particular
Requestors: devendra.singh [...] lsi.com
Cc:
AdminCc:

Bug Information
Severity: Important
Broken in: (no value)
Fixed in: (no value)



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The read_file subroutine generates error when parameters are defined with module declaration as shown in the example below: module #(parameter a = 1'b0, parameter b = 2'b00) (input reset, input clk, output otr); ...... .... endmodule Also when list of nets is generated for a particular module, it also contains the parameters.
You're missing the module name. When I add it, and use the latest version I get what I think is correct, if not please send me the output you get and how you got it. Also, it's correct that parameters are listed under nets, it would be better if they were labeled "identifiers". I'll document that. module test #(parameter a = 1'b0, parameter b = 2'b00) (input reset, input clk, output otr); endmodule + verilog/parser_bugs.v:203: MODULE 'module' 'v2kparam' undef '0' + verilog/parser_bugs.v:204: SIGNAL_DECL 'parameter' 'a' '' '' '' '1'b0' + verilog/parser_bugs.v:205: SIGNAL_DECL 'parameter' 'b' '' '' '' '2'b00' + verilog/parser_bugs.v:206: SIGNAL_DECL 'input' 'reset' '' '' '' '' + verilog/parser_bugs.v:206: PORT 'reset' + verilog/parser_bugs.v:207: SIGNAL_DECL 'input' 'clk' '' '' '' '' + verilog/parser_bugs.v:207: PORT 'clk' + verilog/parser_bugs.v:208: SIGNAL_DECL 'output' 'otr' '' '' '' '' + verilog/parser_bugs.v:208: PORT 'otr' + verilog/parser_bugs.v:203: ENDMODULE 'endmodule'
Subject: parameter parse error
From: devendra.singh [...] lsi.com
Download (untitled) / with headers
text/plain 1.5k
Please download all the files attached in a directory and run vp15.pl This will generate following error ######################################### %Error: i2c_blk_ver.v:2: syntax error, unexpected parameter, expecting IDENTIFIER Exiting due to errors ######################################### If you remove the parameter declaration, it goes through well. But there is one more query if you see the generated log, nets connected to array ports(width>1) does not contain array attribute value. On Mon Oct 22 08:36:02 2007, WSNYDER wrote: Show quoted text
> You're missing the module name. When I add it, and use the latest > version I get what I think is correct, if not please send me the output > you get and how you got it. Also, it's correct that parameters are > listed under nets, it would be better if they were labeled > "identifiers". I'll document that. > > module test > #(parameter a = 1'b0, > parameter b = 2'b00) > (input reset, > input clk, > output otr); > endmodule > > + verilog/parser_bugs.v:203: MODULE 'module' 'v2kparam' undef '0' > + verilog/parser_bugs.v:204: SIGNAL_DECL 'parameter' 'a' '' '' '' '1'b0' > + verilog/parser_bugs.v:205: SIGNAL_DECL 'parameter' 'b' '' '' '' '2'b00' > + verilog/parser_bugs.v:206: SIGNAL_DECL 'input' 'reset' '' '' '' '' > + verilog/parser_bugs.v:206: PORT 'reset' > + verilog/parser_bugs.v:207: SIGNAL_DECL 'input' 'clk' '' '' '' '' > + verilog/parser_bugs.v:207: PORT 'clk' > + verilog/parser_bugs.v:208: SIGNAL_DECL 'output' 'otr' '' '' '' '' > + verilog/parser_bugs.v:208: PORT 'otr' > + verilog/parser_bugs.v:203: ENDMODULE 'endmodule'
Download uC_interface.v
application/octet-stream 14.5k

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Download upcnt4.v
application/octet-stream 2k

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Download i2c_control.v
application/octet-stream 33.9k

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Download vp15.pl
text/x-perl 1.8k
#!/usr/bin/perl -w use Verilog::Netlist; use XML::Simple qw(XMLout); # Setup options so files can be found use Verilog::Getopt; my $opt = new Verilog::Getopt; $opt->parameter( "+incdir+", "-y ./","+libext+.v", ); # Prepare netlist my $netlist = new Verilog::Netlist (options => $opt,); foreach my $file ('i2c_blk_ver.v') { $netlist->read_file (filename=>$file); } # Read in any sub-modules $netlist->link(); $netlist->lint(); $netlist->exit_if_error(); # Find top module my @top_module = $netlist->top_modules_sorted; print $top_module[0]->name."\n"; my $module = $netlist->find_module($top_module[0]->name); # Extract the list of instances under top module my @cells = $module->cells; foreach my $mod ($netlist->top_modules_sorted) { show_hier ($mod, " ", "", ""); } sub show_hier { my $mod = shift; my $indent = shift; my $hier = shift; my $cellname = shift; if (!$cellname) {$hier = $mod->name;} #top modules get the design name else { printf ("%-45s %s\n", $indent."Module ".$mod->name,$hier) if($mod->name eq "SHIFT8"); $hier .= ".$cellname";} #append the cellname ##Printing cell pin list foreach my $cell ($mod->cells_sorted) { if ($cell->submodname eq "SHIFT8"){ printf ($indent. " Module %s\n", $cell->submodname); printf ($indent. " Cell %s\n", $cell->name); foreach my $pin ($cell->pins_sorted) { printf ($indent." .%s(%s)\n", $pin->name, $pin->netname); $pin->dump; ## print "pin name ".$nt->name."\n"; } } show_hier ($cell->submod, $indent." ", $hier, $cell->name) if $cell->submod; } }
Download i2c_blk_ver.v
application/octet-stream 5.3k

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Download SHIFT8.v
application/octet-stream 2.3k

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Subject: Attached case works in recent versions of Verilog-Mode
Long ago resolved.


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