Skip Menu |

Preferred bug tracker

Please visit the preferred bug tracker to report your issue.

This queue is for tickets about the Verilog-Perl CPAN distribution.

Report information
The Basics
Id: 28496
Status: resolved
Worked: 5 min
Priority: 0/
Queue: Verilog-Perl

Owner: Nobody in particular
Requestors: vananth [...]

Bug Information
Severity: (no value)
Broken in: (no value)
Fixed in: (no value)

Subject: Verilog Perl does not parse widths correctly
Date: Thu, 26 Jul 2007 15:24:39 -0700
To: <bug-Verilog-Perl [...]>
From: "Vinod Ananth" <vananth [...]>
Download (untitled) / with headers
text/plain 465b
Hi, I found the following problem when trying to parse a Verilog file using Verilog::Netlist One of the ports in the module is defined like this input [32-1:0] DATA_IN; When the parser hits that line, it prints the following message Argument "32-1" isn't numeric in subtraction (-) at <lib path>/ line 35 (This is valid Verilog syntax though) When I then try to get the width of this signal, it shows 33 instead of 32. Thanks Vinod

This service is sponsored and maintained by Best Practical Solutions and runs on infrastructure.

Please report any issues with to