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This queue is for tickets about the Verilog-Perl CPAN distribution.

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The Basics
Id: 27072
Status: resolved
Priority: 0/
Queue: Verilog-Perl

Owner: Nobody in particular
Requestors: nodine [...]

Bug Information
Severity: Normal
Broken in: 2.373
Fixed in: 3.000

Subject: output reg declaration should call signal_decl twice
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In the attached file, the declaration output reg sum; should be interpreted as if it had been output sum; reg sum; In other words, Verilog::SigParser should call signal_decl twice, once with keyword "output" and once with keyword "reg".
Subject: pr693.v
Download pr693.v
application/tkgate 580b

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