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This queue is for tickets about the Verilog-Perl CPAN distribution.

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The Basics
Id: 27045
Status: resolved
Priority: 0/
Queue: Verilog-Perl

People
Owner: Nobody in particular
Requestors: nodine [...] cpan.org
Cc:
AdminCc:

Bug Information
Severity: Normal
Broken in: 2.373
Fixed in: 3.000



Subject: signal_decl not called for definitions in port list
Download (untitled) / with headers
text/plain 241b
None of the signals for module "ansireg" in the attached file have signal_decl called for them by Verilog::SigParser. They are defined in the module statement itself: module ansireg(input clk, reset, input [7:0] d, output reg [7:0] q );
Subject: port-test7.v
Download port-test7.v
application/tkgate 781b

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