|Subject:||Verilog::Preproc requires newline at end of file|
Verilog::Preproc returns an error %Error: ../testsuite/no_newline.v:1: EOF (missing return?) in define value because there is no newline at the end of file. One of the source verilog files in a common commercially licensed core has this issue. There should be some option that allows suppressing this error.
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