| Subject: | Verilog::Preproc requires newline at end of file |
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Verilog::Preproc returns an error
%Error: ../testsuite/no_newline.v:1: EOF (missing return?) in define value
because there is no newline at the end of file. One of the source
verilog files in a common commercially licensed core has this issue.
There should be some option that allows suppressing this error.
| Subject: | no_newline.v |
| MIME-Version: | 1.0 |
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| Content-Type: | application/tkgate; name="no_newline.v" |
| Content-Disposition: | inline; filename="no_newline.v" |
| Content-Transfer-Encoding: | base64 |
| Content-Length: | 14 |
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