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This queue is for tickets about the Verilog-Perl CPAN distribution.

Report information
The Basics
Id: 26999
Status: rejected
Priority: 0/
Queue: Verilog-Perl

People
Owner: Nobody in particular
Requestors: nodine [...] cpan.org
Cc:
AdminCc:

Bug Information
Severity: Normal
Broken in: 2.373
Fixed in: (no value)



Subject: Verilog::Preproc requires newline at end of file
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Verilog::Preproc returns an error %Error: ../testsuite/no_newline.v:1: EOF (missing return?) in define value because there is no newline at the end of file. One of the source verilog files in a common commercially licensed core has this issue. There should be some option that allows suppressing this error.
Subject: no_newline.v
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The IEEE spec states in 19.3.1 that "The first newline not preceeded by a backslash shall end the macro text." Since their define never has a newline, their code is wrong. I don't want to add options to parse code that violates the spec and is also exceedingly uncommon (since I've only seen it once ever.) Sorry.
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Subject: Re: [rt.cpan.org #26999] Verilog::Preproc requires newline at end of file
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That's reasonable. I guess we should report the error to the company that produced the Verilog. Thanks.


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